Control of Flyback Converters

## ELECTENG 311
# Electronics Systems Design 
### Closed Loop Controller Design

.TitleAuthor[Duleepa J Thrimawithana]

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.logo-slide[]
.footer[[Duleepa J Thrimawithana](https://www.linkedin.com/in/duleepajt), Department of Electrical, Computer and Software Engineering (2021)]

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# Learning Objectives

- Why do we need closed loop control? 
- Behavior of a closed loop controller
 - Steady-state error 
 - Impact of gain on steady-state error
 - Stability of the controller
- PI controllers 
- Peak current mode control 
- UC3843 control IC
 - Functional diagram of a UC3843
 - How is peak current mode control achieved?
 - How to setup the oscillator?
 - How do we provide a feedback of current?

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# Closed-Loop Control
### An Introduction

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.logo-slide[]
.footer[[Duleepa J Thrimawithana](https://www.linkedin.com/in/duleepajt), Department of Electrical, Computer and Software Engineering (2021)]

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name: S2

# Open-Loop Control (PI)

- If we know precise details of our flyback converter, then for example, using a microcontroller we can generate the correct D for the switch to achieve our target output
 - We call this type of control **open-loop control** as we do not monitor the converter to deduce D we should be operating at
- In real life, component values are not exact and the load resistance will change, making it impossible to know D needed for a specific Vout [since](https://uoa-ee311.github.io/presentations/AnalogL1/presentation.html#23),
\\[ V\_{out} = \sqrt{ {R\_{Load}}/ \left({2f\_s L\_p} \right) } \, V\_{in}D \\]

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name: S3

# Open-Loop Control (PII)

- A flyback can be modelled as a black box, which takes D as the input and produce Vout as the output
- In the simplest form, ignoring the impact of energy storage elements, this black box mathematically can be represented as a transfer function, Tflybk, where, 
\\[ \frac {V\_{out}} {D} = \sqrt{ \frac {R\_{Load}} {2f\_s L\_p} } \, V\_{in} = T\_{flybk} \\]
- As an example, if RLoad changes by twice then Vout will change by 1.41 times unless we change D

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# Demo: Open-Loop Control

.questions[
Lets consider the same flyback converter from previous lecture where Vin=20V, Lp=5µH, fs=100kHz and Rload=100Ω. If D is held at 0.5 by a microcontroller then it will be generating a 100V output. What will be the output if Rload increases to 200Ω? Is there a way for the microcontroller to learn the load has changed?
]

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# Closed-Loop Control & Feedback

- One way to know if the load or other circuit parameters that impacts Vout has changed is to measure Vout and use this information inside the microcontroller to help deduce an appropriate D to use
 - This means we monitor and use Vout as a **feedback** to **control** Vout
 - We call this type of control **closed-loop** control
- There are many ways to use Vout feedback to derive D but it is not a straightforward task
- This is because Vout is not only a function of Rload but it also depends on other circuit parameters
 - A feedback of just only Vout would not tell us which of those parameters have changed

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# Error Voltage

- As the first step, we can compare the feedback of Vout with our target or the **reference** Vout, Vref, to determine if D needs to be increased or reduced
 - Vref - Vout is referred to as the **error voltage**, Verr
- Note that Vout is directly proportional to D in a flyback converter
 - A negative Verr therefore tells that D needs to be reduced
 - A positive Verr therefore tells that D needs to be increased
- How do we deduce by how much to reduce/increase D by?

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# Proportional Controller

- Since Vout is proportional to D, we can apply a **proportional gain**, Kp to Verr to deduce an approximate D
- Looking at [Tflybk](#S3) we could see that the proportion D needs to be change by depends on which parameter changed
- To find which value of Kp to use, lets express Vout as a function of Kp
\\[ V\_{out} = V\_{err} K\_{p} T\_{flybk} = \left( V\_{ref} - V\_{out} \right) K\_{p} T\_{flybk} \quad \Rightarrow \quad V\_{out} = V\_{ref} \frac {K\_p T\_{flybk}} {1 + K\_p T\_{flybk}} \\]

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# Proportional Gain - Kp

- From our [analysis](#S7), we could see that if Kp is chosen to be large such that KpTflybk >> 1, then Vout ≈ Vref
- We could also observe this in our system diagram where D = KpVerr
 - Since 0 ≤ D ≤ 1, larger the Kp smaller the Verr
- Thus, a proportional controller with a sufficiently large Kp will help achieve an Vout that closely follow a target voltage set by Vref
- How large can Kp be and would there be any adverse issues using a large Kp?

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# Demo: Closed-Loop Proportional Control

.questions[
Lets consider the same flyback converter where Vin=20V, Lp=5µH, fs=100kHz and Rload=100Ω. The simplified Tflybk we derived ignoring the impact of energy storage elements thus equates to 200. In your design, the user will set Vref to program the required Vout. Explore how Kp impacts the ability of Vout to follow Vref. If Rload doubles, how much does Verr change by?
]

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# Instability (PI)

- Vref can be modelled as a sinusoidal signal to emulate a user changing Vref to set different Vout values
 - Disturbances we make to the system, e.g., changing Vref or Rload, can be considered to generate a spectrum of frequencies 
- In a real flyback converter, to store energy in Lp and to charge/discharge Co takes time, and thus a change in D does not result in an immediate change in Vout
 - The oversimplified Tflybk ignored these delays
- Lets exaggerate these delays and assume that at the frequency of Vref the flyback converter introduce a half-cycle delay (i.e. 1800 delay)
 - A 1800 delay to a sinusoidal wave represents a negative gain
- Thus, Tflybk at this specific frequency can be written as -Tflybk
 - Note, |Tflybk| at this frequency might be much less than,
 \\[ T\_{flybk} = \sqrt{ {R\_{Load}} / ({2f\_s L\_p} }) \, V\_{in} \\]

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name: S11

# Instability (PII)

- We can express Vout under the specific conditions mentioned in the previous slide,
\\[ V\_{out} = -V\_{ref} \frac {K\_p T\_{flybk}} {1 - K\_p T\_{flybk}} \\]
- From this analysis we can see that Vout tends to infinity when KpTflybk approaches 1
- Thus to ensure the closed-loop controlled system is **stable**, Kp needs to be sufficiently small and satisfy KpTflybk < 1, if Tflybk introduce a 1800 delay at a certain frequency
 - In real life, Tflybk will have a frequency dependent gain and a phase

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# Demo: Instability

.questions[
Lets consider the same flyback converter where Vin=20V, Lp=5µH, fs=100kHz and Rload=100Ω. Vref is modelled as a sinusoidal wave with a 1kHz frequency to represent a user requesting different Vout values. Lets assume Tflybk is -10 at 1kHz. Explore how Kp impacts the stability of the system. 
]

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# Sensitivity to Noise

- A flyback converter, like any other SMPS, generate significant electromagnetic noise during operation
- In addition, Vout itself has a ripple across it that results from the physical nature of the circuit
- A larger Kp can amplify these unwanted components to a point that they interfere with the closed-loop controller operation
 - Both the noise and Vout ripple components couples in with the closed-loop controller mainly though the feedback signal
- The selected Kp must ensure the system is not reacting to noise

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# Integral Controller

- With a proportional controller, we cannot ensure that Vout is exactly the same as Vref (i.e., Verr = 0)
- To avoid this drawback, we can employ an integral controller, which derives D by integrating Verr over time
\\[ D = K\_i \int {V\_{err}} \, \mathrm{d}t \\]
- D settles at the correct value as the integrator accumulates the error until Verr = 0

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# Integral Gain - Ki

- Regardless what the **integral gain**, Ki, is set to, an integral controller achieves 0 steady-state error
 - A larger Ki helps the controller to reach steady-state faster 
- An integral controller introduces a 900 phase delay into the system
 - Together with the phase delay introduced by the flyback converter, this could lead to system reaching instability faster 
- Care must be taken to ensure the system is stable when using an integral controller

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# Demo: Integral Controller

.questions[
Lets consider the same flyback converter where Vin=20V, Lp=5µH, fs=100kHz and Rload=100Ω. In your design, the user will set Vref to program the required Vout. Explore how Ki impacts the performance of the controller under a few different Vref and Rload settings.
]

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name: S17

# Proportional Integral Controller (PI)

- We can combine the proportional and the integral controllers to implement a much better controller
 - This type of controllers are referred to as Proportional Integral or **PI** controllers
- Kp sets the **proportional gain** while Ki sets the **integral gain**
\\[ D = K\_p V\_{err} + K\_i \int {V\_{err}} \, \mathrm{d}t \\]
- Increasing Kp and Ki helps Vout to reach towards the target faster but can create overshoot

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# Proportional Integral Controller (PII)

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- Though the integral term in a PI eliminates steady-state error, it adds a phase delay to the system pushing it towards instability 
 - Larger Ki thus lead to longer settling time
- To understand how Kp and Ki impacts the closed-loop operation, we can use the S-domain transfer function of a PI controller, 
\\[ D = K\_p V\_{err} + \frac {K\_i } {s} V\_{err} \quad \Rightarrow \quad \frac {D} {V\_{err}} = T\_{PI} = K\_p + \frac {K\_i } {s} \\]
- To help sketch TPI bode plot, we can rewrite as,
\\[ T\_{PI} = K\_p \frac { s + K\_i / K\_p} {s} = K\_p \frac { s + \omega\_z } {s} \quad \text {where} \quad \omega\_z = \frac {K\_i} {K\_p} \\]
- ωz sets the frequency at which phase delay drops to 00 
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# Demo: PI Controller

.questions[
Lets consider the same flyback converter where Vin=20V, Lp=5µH, fs=100kHz and Rload=100Ω. In your design, the user will set Vref to program the required Vout. Explore how Ki and Kp impacts the performance of the controller under a few different Rload settings. Here, we are stepping Vref from 100V to 150V at 0.5s.
]

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# Peak Current Model Controller (PI)

- Our [analysis of a flyback converter](https://uoa-ee311.github.io/presentations/AnalogL1/presentation.html#16) showed that ILp(pk) is proportional to D
\\[ I\_{Lp(pk)} = \frac{V\_{in}}{L\_p} DT\_{s} \quad \Rightarrow \quad D = \frac {f\_s L\_p} {V\_{in}} I\_{Lp(pk)} \\]
- As such, instead of directly controlling D, we can control ILp(pk) to achieve a similar outcome
 - This is **peak current mode control** and is a very common/preferred control method 
- The output of the PI controller now sets the reference peak current, ILp(pk)_ref

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# Peak Current Model Controller (PII)

- A comparator is commonly used to compare ILp fed to its non-inverting input with ILp(pk)_ref fed to its inverting input
 - When ILp rises above ILp(pk)_ref, comparator outputs 0 indicating switch should be turned-off
- A latch is typically used to hold the off-state of the switch until the end of the time-period 
 - An oscillator connected to the latch sets the switching frequency
- Since ILp(pk) provide additional information we can now improve the functionality (e.g., implement input over current protection)

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# The UC3843 Controller IC
### Operating Principles

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.logo-slide[]
.footer[[Duleepa J Thrimawithana](https://www.linkedin.com/in/duleepajt), Department of Electrical, Computer and Software Engineering (2021)]

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name: S22

# Proposed Controller Implementation

- In your project, we will use a UC3843 peak current mode controller IC to drive Sp in order to generate Vout requested by the user
- The PI controller will be implemented on an ATmega328PB and it will generate ILp(pk)_ref for the UC3843
 - Since ATmega328PB does not have a digital-to-analog converter (DAC), we will use its PWM unit with an RC filter to implement a DAC

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# UC3843 Functional Diagram

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# Internal Power Supply Circuitry

- To power the IC connect a voltage source between VCC (+) and GNG (-) pins 
 - Needs to be more than 8.4V as the undervoltage lockout (UVLO) protection will otherwise turn-off due to insufficient input voltage
 - Input voltage needs to be less than 30V to avoid damaging the IC
 - 15V to 20V is a good input voltage to aim for
- IC generates its own 5V to power internal circuitry and this is also available at VREF
- IC also generate its own 2.5V as a reference but this is not made available for us to use

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# Output Circuitry

- We call this output circuit configuration a **Totem Pole** or a **Push-Pull** configuration
 - OUTPUT pin can be connected directly to the gate of the MOSFET switch used in our flyback converter through a small resistor
 - This resistor limits the current drawn from OUTPUT pin to less than 1A
- The output of the control circuitry determines if the OUTPUT pin is 0V or VCC
 - If control circuitry sends logic '1' OUTPUT is 0V (i.e., MOSFET switch is off)
 - If control circuitry sends logic '0' OUTPUT is VCC (i.e., MOSFET switch is on)

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# Control Circuitry - Oscillator

- Connecting a resistor, RT, and a capacitor, CT, at the RT/CT pin configures the oscillator to operate at the required PWM frequency, fs
- Voltage at the RT/CT pin is a sawtooth waveform that has a frequency fs
 - Every time this sawtooth waveform reach its peak voltage the oscillator generates an output pulse that 'sets' the PWM latch
- When PWM latch is 'set' it outputs logic '0' making the 'OR' gate output a logic '0' causing MOSFET switch of the flyback converter to turn-on

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# Selecting RT & CT Values

- The values of RT and CT determines fs (i.e., PWM frequency)
- The [datasheet](https://www.ti.com/lit/ds/symlink/uc3843.pdf?ts=1627207030483&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FUC3843) provides a plot that shows the relation between RT, CT and fs
 - E.g., To setup a 100kHz we can use a 1nF capacitor for CT and approximately a 18kΩ resistor for RT
- Once you connect the selected RT and CT, the UC3843 will generate a PWM signal at the OUTPUT pin
 - The duty-cycle, D, of this PWM signal is controlled by the internal comparator that compares ILp with ILp(pk)_ref we generate from the ATmega328PB

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# Control Circuitry - OpAmp (PI)

- The UC3843 has an internal OpAmp to produce ILp(pk)_ref at the inverting input to the comparator
 - Though we don't need it for our design, we cannot by pass it
- The non-inverting terminal of this OpAmp is supplied internally with 2.5V
- The inverting terminal, VFB, is available for us to configure it as an inverting amplifier
 - We do this by connecting resistors Rop1 and Rop2
- We will supply the PI controller output coming from the ATmega328PB to this OpAmp through Rop1

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# Control Circuitry - OpAmp (PII)

- The output of the OpAmp, Vpi_out, is a scaled version of Vpi_in generated by the ATmega328PB,

\\[ V\_{pi\\\_out} = 2.5 + \left( 2.5 - V\_{pi\\\_in} \right) R\_{op2}/R\_{op1} \\]

- The output from our ATmega328PB (i.e., Vpi_in) is going to be in the range 1V to about 4V
 - So lets set Rop1 = 4.7kΩ and Rop2 = 10kΩ in our project (i.e., Vpi_out = 7.8V - 2.1Vpi_in)
 - In this case Vpi_out changes roughly from 0V to 5V when Vpi_in changes from 4V to 1V

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# Control Circuitry - Comparator (PI)

- 1.4V is subtracted from Vpi_out and divided by 3 before feeding to the inverting input of comparator
 - This sets ILp(pk)_ref and its maximum value is clamped to 1V by a Zener diode 
- When the voltage at ISENS pin exceeds ILp(pk)_ref, the comparator outputs 1 to reset the latch
 - When PWM latch is 'reset' it outputs logic '1' making the 'OR' gate output a logic '1' causing MOSFET switch of the flyback converter to turn-off
- When the PI controller output, Vpi_in is 1V (i.e., Vpi_out ≈ 5V), ILp(pk)_ref will be 1V

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# Control Circuitry - Comparator (PII)

- When the PI controller output, Vpi_in is 4V (i.e., Vpi_out ≈ 0V), ILp(pk)_ref will be 0V 
 - This means ILp(pk)_ref will be a value between 0V and 1V 
- However, in the generic current mode controller implementation we investigated [earlier](#S21) a larger Vpi_in should result in a larger peak current
- This issue is introduced because Vpi_in goes through the inverting OpAmp in the UC3843 
 - We can account for this in our ATmega328PB program

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# Designing the Current Sensor (PI)

.left-column-50[
<img src="img/CurrentSens.png" height="400px">
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- A measurement of ILp needs to be provided at the ISENS pin to enable UC3843 to control ILp(pk)
- A current sense resistor, Ri, can be used to measure Iin, which is the same as ILp,
\\[ V\_{ILp} = I\_{in}R\_i = I\_{Lp}R\_i \\]
- Since the maximum value of ILp(pk)_ref is 1V, the **maximum ILp(pk)** allowed is,

\\[ I\_{Lp(pk)\\\_{max}} = 1 / R\_i \\]
- We should design ILp(pk)_max to be larger than maximum ILp(pk) of our design
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# Designing the Current Sensor (PII)

.left-column-50[
<img src="img/CurrentSensF.png" height="400px">
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- VILp measurement in practice will have a significant noise content
- A RC lowpass filter is used to filter this noise before feeding VILp to ISENSE
- Filter needs to pass ILp, which is at fs, without attenuation
 - So the cutoff frequency of the filter could be at about 100 times fs
\\[ \frac {1} {2 \pi R\_{if}C\_{if} } \geqslant 100f\_s \\]
- For practical reasons Cif should be 100pF or larger
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# The Recommended Design
.zoom15[
.center[<img src="img/Design.png" height="450px">]
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# Improvements to Consider

- While keeping fs at 100kHz, can we reduce the size of the transformer? 
 - How small can it be?
- Can we reduce the loss in Ri?
 - What options are there to reduce loss in Ri?
- Do we need the isolated power module, U2, to power the ATmega328PB?
 - Can we not power it from Vout?
- Why is the ATmega328PB on the isolated side of the circuit?
 - Would the design simplifies if the ATmeag328PB is on the input side of the circuit?
- Do we need the digital isolator, IC1, in the design?
 - Are there cost effective alternatives? 
- Can we design the circuit without the digital isolator?
 - If so how can we isolate the Vout measurement?
- What other improvements can we do?

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# Questions?